KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Commercial Grade
SHARC D.
Super Harvard Architecture
Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O
32-bit IE.
......... 3 SHARC Family Core Architecture ........ 3 Memory and I/O Interface Features ....... 4 Porting Code From the ADSP-21060 or ADSP-21062 ... 7 Development Tools ....... 7 Additional Information .. 8 Related Signal Chains .... 8
Pin Function D.
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